From 6b3f8155ea875b6a837facc934b3b193aa5e4ddc Mon Sep 17 00:00:00 2001
From: OBarronCS <55004530+OBarronCS@users.noreply.github.com>
Date: Wed, 22 May 2024 04:25:16 -0700
Subject: [PATCH] Don't re-resolve register value - riscv5 (#2177)

---
 pwndbg/disasm/riscv.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/pwndbg/disasm/riscv.py b/pwndbg/disasm/riscv.py
index 0506f816d..7500a6cda 100644
--- a/pwndbg/disasm/riscv.py
+++ b/pwndbg/disasm/riscv.py
@@ -20,10 +20,10 @@ class DisassemblyAssistant(pwndbg.disasm.arch.DisassemblyAssistant):
         self, instruction: PwndbgInstruction, emu: Emulator | None
     ) -> InstructionCondition:
         # B-type instructions have two source registers that are compared
-        src1_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)
+        src1_unsigned = instruction.op_find(CS_OP_REG, 1).before_value
         # compressed instructions c.beqz and c.bnez only use one register operand.
         if instruction.op_count(CS_OP_REG) > 1:
-            src2_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 2), emu)
+            src2_unsigned = instruction.op_find(CS_OP_REG, 2).before_value
         else:
             src2_unsigned = 0
 
@@ -96,7 +96,7 @@ class DisassemblyAssistant(pwndbg.disasm.arch.DisassemblyAssistant):
         # Determine the target address of the indirect jump
         if instruction.id in [RISCV_INS_JALR, RISCV_INS_C_JALR]:
             target = (
-                self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)
+                instruction.op_find(CS_OP_REG, 1).before_value
                 + instruction.op_find(CS_OP_IMM, 1).imm
             ) & ptrmask
             # Clear the lowest bit without knowing the register width